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Updates found with 'communications'

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Updates found with 'communications'

VLSI PROJECTS ABSTRACT 2016-2017 ALGORITHM AND ARCHITECTURE OF CONFIGURABLE JOINT DETECTION AND DECODING FOR MIMO WIRELESS COMMUNICATIONS WITH CONVOLUTION CODES ABSTRACT: This paper presents an algorithm and a VLSI architecture of a configurable joint detection and decoding (CJDD) scheme for multi-input multi-output (MIMO) wireless communication systems with convolutional codes. A novel tree-enumeration strategy is proposed such that the MIMO detection and decoding of convolutional codes can be conducted in single stage using a tree-searching engine. Moreover, this design can be configured to support different combinations of quadrature amplitude modulation (QAM) schemes as well as encoder code rates, and thus can be more practically deployed to real-world MIMO wireless systems. A formal outline of the proposed algorithm will be given and simulation results for 16-QAM and 64-QAM with rate-1/2 and rate-1/3 codes will be presented showing that, compared with the conventional separate scheme, the CJDD algorithm can greatly improve bit error rate (BER) performance with different system settings. In addition, the VLSI architecture and implementation of the CJDD approach will be illustrated. The architectures and circuits are designed to support configurability and flexibility while maintaining high efficiency and low complexity. The post layout experimental results for 16-QAM and 64-QAM with rate-1/2 and rate-1/3 codes show that, compared with the previous configurable design, this architecture can achieve reduced or comparable complexity with improved BER performance. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.EXISTING SYSTEM: We will briefly review the system model of MIMO communications and tree-searching type MIMO detection schemes. In addition, we will give an introductory overview for the fundamental concept of joint MIMO detection and decoding of convolutional codes. PROPOSED SYSTEM: The essential concept of the proposed CJDD algorithm lies in an innovative tree-enumeration scheme such that the number of tree levels that must be considered together before moving forward can be configured through system settings, including modulation scheme as well as encoder code rate. Therefore, under various transmission conditions, different modulations and/or coding rates could be chosen, and thus the operation for the CJDD can be adjusted accordingly. Before formally outlining the proposed algorithm, in this section, we summarize the system settings that might change the tree-searching behavior and explicitly define the control parameters that are used to configure the operation of the algorithm.ADVANTAGES:• improve the BER performance• improve the design efficiency• reduced system complexityDISADVANTAGES:• BER performance is low• efficiency of the design is low• complex system SOFTWARE IMPLEMENTATION:• Modelsim• Xilinx ISE
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VLSI PROJECTS ABSTRACT 2016-2017 FAULT TOLERANT PARALLEL FFTS USING ERROR CORRECTION CODES AND PARSEVAL CHECKS ABSTRACT: Soft errors pose a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for many applications. Communications and signal processing systems are no exceptions to this trend. For some applications, an interesting option is to use algorithmic-based fault tolerance (ABFT) techniques that try to exploit the algorithmic properties to detect and correct errors. Signal processing and communication applications are well suited for ABFT. One example is fast Fourier transforms (FFTs) that are a key building block in many systems. Several protection schemes have been proposed to detect and correct errors in FFTs. Among those, probably the uses of the Parseval or sum of squares check is the most widely known. In modern communication systems, it is increasingly common to find several blocks operating in parallel. Recently, a technique that exploits this fact to implement fault tolerance on parallel filters has been proposed. In this brief, this technique is first applied to protect FFTs. Then, two improved protection schemes that combine the use of error correction codes and Parseval checks are proposed and evaluated. The results show that the proposed schemes can further reduce the implementation cost of protection. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.EXISTING SYSTEM: Signal processing and communications circuits are well suited for ABFT as they have regular structures and many algorithmic properties. Over the years, many ABFT techniques have been proposed to protect the basic blocks that are commonly used in those circuits. Several works have considered the protection of digital filters. For example, the use of replication using reduced precision copies of the filter has been proposed as an alternative to TMR but with a lower cost. The knowledge of the distribution of the filter output has also been recently exploited to detect and correct errors with lower overheads. The protection of fast Fourier transforms (FFTs) has also been widely studied. As signal-processing circuits become more complex, it is common to find several filters or FFTs operating in parallel. This occurs for example in filter banks or in multiple-input multiple-output (MIMO) communication systems. In particular, MIMO orthogonal frequency division modulation (MIMO-OFDM) systems use parallel iFFTs/FFTs for modulation/demodulation. MIMO-OFDM is implemented on long-term evolution mobile systems and also on WiMax. The presence of parallel filters or FFTs creates an opportunity to implement ABFT techniques for the entire group of parallel modules instead of for each one independently. This has been studied for digital filters initially in where two filters were considered. More recently, a general scheme based on the use of error correction codes (ECCs) has been proposed. In this technique, the idea is that each filter can be the equivalent of a bit in an ECC and parity check bits can be computed using addition. This technique can be used for operations, in which the output of the sum of several inputs is the sum of the individual outputs. This is true for any linear operation as, for example, the discrete Fourier transform (DFT). PROPOSED SYSTEM: The two proposed techniques provide new alternatives to protect parallel FFTs that can be more efficient than protecting each of the FFTs independently. The proposed schemes have been evaluated using FPGA implementations to assess the protection overhead. The results show that by combining the use of ECCs and Parseval checks, the protection overhead can be reduced compared with the use of only ECCs as proposed. Fault injection experiments have also been conducted to verify the ability of the implementations to detect and correct errors.ADVANTAGES:• Improve error detection capabilities and reduce complexity.SOFTWARE IMPLEMENTATION• Modelsim• Xilinx ISE
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JAVA/DOT NET PROJECTS ABSTRACT 2016-2017 PROVIDING USER SECURITY GUARANTEES IN PUBLIC INFRASTRUCTURE CLOUDS ABSTRACT: The infrastructure cloud (IaaS) service model offers improved resource flexibility and availability, where tenants – insulated from the minutiae of hardware maintenance – rent computing resources to deploy and operate complex systems. Large-scale services running on IaaS platforms demonstrate the viability of this model; nevertheless, many organizations operating on sensitive data avoid migrating operations to IaaS platforms due to security concerns. In this paper, we describe a framework for data and operation security in IaaS, consisting of protocols for a trusted launch of virtual machines and domain-based storage protection. We continue with an extensive theoretical analysis with proofs about protocol resistance against attacks in the defined threat model. The protocols allow trust to be established by remotely attesting host platform configuration prior to launching guest virtual machines and ensure confidentiality of data in remote storage, with encryption keys maintained outside of the IaaS domain. Presented experimental results demonstrate the validity and efficiency of the proposed protocols. The framework prototype was implemented on a test bed operating a public electronic health record system, showing that the proposed protocols can be integrated into existing cloud environments.SYSTEM ANALYSISEXISTING SYSTEM The protocols allow trust to be established by remotely attesting host platform configuration prior to launching guest virtual machines and ensure confidentiality of data in remote storage, with encryption keys maintained outside of the IaaS domain. Presented experimental results demonstrate the validity and efficiency of the proposed protocols. The framework prototype was implemented on a test bed operating a public electronic health record system, showing that the proposed protocols can be integrated into existing cloud environments.PROPOSED SYSTEM: Presented an IaaS storage protection scheme addressing access control. The authors analyse access rights management of shared versioned encrypted data on cloud infrastructure for a restricted group and propose a scalable and flexible key management scheme. Access rights are represented as a graph, making a distinction between data encryption keys and encrypted updates on the keys and enabling flexible join/leave client operations, similar to properties presented by the protocols in this paper. Despite its advantages, the requirement for client-side encryption limits the applicability of the scheme in and introduces important functional limitations on indexing and search. In our model, all cryptographic operations are performed on trusted IaaS compute hosts, which are able to allocate more computational resources than client devices.Abundant works have been proposed under different threat models to achieve various search functionality, SYSTEM SPECIFICATIONHardware Requirements:• System : Pentium IV 2.4 GHz.• Hard Disk : 40 GB.• Floppy Drive : 1.44 Mb.• Monitor : 14’ Colour Monitor.• Mouse : Optical Mouse.• Ram : 512 Mb.Software Requirements:• Operating system : Windows 7 Ultimate.• Coding Language : ASP.Net with C#• Front-End : Visual Studio 2012 Professional.• Data Base : SQL Server 2008.CONCLUSION: From a tenant point of view, the cloud security model does not yet hold against threat models developed for the traditional model where the hosts are operated and used by the same organization. However, there is a steady progress towards strengthening the IaaS security model. In this work we presented a framework for trusted infrastructure cloud deployment, with two focus points: VM deployment on trusted compute hosts and domain-based protection of stored data. We described in detail the design, implementation and security evaluation of protocols for trusted VM launch and domain-based storage protection. The solutions are based on requirements elicited by a public healthcare authority, have been implemented in a popular open-source IaaS platform and tested on a prototype deployment of a distributed EHR system. In the security analysis, we introduced a series of attacks and proved that the protocols hold in the specified threat model. To obtain further confidence in the semantic security properties of the protocols, we have modelled and verified them with ProVerif. Finally, our performance tests have shown that the protocols introduce a insignificant performance overhead. This work has covered only a fraction of the IaaS attack landscape. Important topics for future work are strengthening the trust model in cloud network communications, data geolocation, and applying searchable encryption schemes to create secure cloud storage mechanisms.
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VLSI PROJECTS ABSTRACT 2016-2017 HIGH-PERFORMANCE NB-LDPC DECODER WITH REDUCTION OF MESSAGE EXCHANGE ABSTRACT: This paper presents a novel algorithm based on trellis min–max for decoding non-binary low-density parity check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.EXISTING SYSTEM: The first algorithm proposed to decode NB-LDPC codes was the Q-ary sum-of-product algorithm (QSPA), which was developed as a generalization of the SPA for binary LDPC codes. Further improvements, such as fast Fourier transform SPA, log-SPA, and max-log-SPA, were proposed to reduce the complexity of the CN processing equations without introducing any performance loss. More recently, a trellisbased implementation for QPSA (T-max-log-QSPA) was proposed, offering a solution that increases the throughput with respect to previous solutions based on QPSA. Its main drawback is that the required area is prohibitive for real applications in communications and storage systems. Extended min-sum (EMS) and min–max algorithms were presented as the approximations of the QSPA, so that they reduce considerably the CN complexity, which only requires additions and/or comparisons. In addition, EMS and min–max algorithms utilize forward–backward metrics to derive the CN output messages. These metrics involve serial computations that limit the throughput of the derived hardware architectures. Trellis EMS (T-EMS) algorithm was proposed with the aim of enabling parallel processing of the messages in the CN. The input messages are organized in a trellis structure, while the output messages are generated in parallel by means of an extra column included in the trellis.PROPOSED SYSTEM: We reformulate the T-MM algorithm as a first step to define our proposal. As can be seen in Algorithm 2, Steps 4 and 5 are the ones reformulated. The function ψ’ in Step 4 obtains, which path in the trellis was used to obtain ΔQ (a), that is, the most reliable path. Considering that a maximum of two deviations is evaluated, the function returns the two GF symbols that define this path, η∗ 1(a) and η∗ 2(a).ADVANTAGES:• Improve area and throughput.DISADVANTAGES:• Area coverage is high• Throughput is low SOFTWARE IMPLEMENTATION• Modelsim• Xilinx ISE
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