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Updates found with 'conventional dipstick'

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Updates found with 'conventional dipstick'

VLSI PROJECTS ABSTRACT 2016-2017 HIGH-SPEED AND ENERGY-EFFICIENT CARRY SKIP ADDER OPERATING UNDER A WIDE RANGE OF SUPPLY VOLTAGE LEVELS ABSTRACT: In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.
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POWER ELECTRONICS ABSTRACT 2016-2017 A LOW CAPACITANCE CASCADED H-BRIDGE MULTI-LEVEL STAT COM ABSTRACT:This paper introduces a cascaded H-bridge multilevel converter (CHB-MC) based Stat Com system that is able to operate with extremely low dc capacitance values. The theoretical limit is calculated for the maximum capacitor voltage ripple, and hence minimum dc capacitance values that can be used in the converter. The proposed low-capacitance Stat Com (LC-Stat Com) is able to operate with large capacitor voltage ripples, which are very close to the calculated theoretical maximum voltage ripple. The maximum voltage stress on the semiconductors in the LC-Stat Com is lower than in a conventional Stat Com system. The variable cluster voltage magnitude in the LC-Stat Com system drops well below the maximum grid voltage, which allows a fixed maximum voltage on the individual capacitors. It is demonstrated that the proposed LC-Stat Com has an asymmetric V-I characteristic, which is especially suited for operation as a reactive power source within the capacitive region. A high-bandwidth control system is designed for the proposed Stat Com to provide control of the capacitor voltages during highly dynamic transient events. The proposed LC-Stat Com system is experimentally verified on a low-voltage 7-level CHB-MC prototype. The experimental results show successful operation of the system with ripples as high as90% of the nominal dc voltage. The required energy storage for the LC-Stat Com system shows significant reduction compared to a conventional Stat Com design.
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POWER ELECTRONICS ABSTRACT 2016-2017 HIGH PERFORMANCE PREDICTIVE CONTROL OF QUASI IMPEDANCE SOURCE INVERTER ABSTRACT:The quasi-Z-source inverter (q ZSI) has attracted much attention for motor drives and renewable energy applications due to its capability to boost or buck in a single converter stage. However, this capability is associated with different challenges related to the closed loop control of currents, control the DC capacitor voltage, produce three-phase AC output current with high dynamic performance and obtain continuous and low ripple input current. This paper presents a predictive control strategy for a three-phase q ZSI that fulfills these requirements without adding any additional layers of control loops. The approach is to improve the overall performance of the converter with a switching strategy that reduces inverter switching losses. The proposed controller implements a discrete-time model of the q ZSI to predict the future behavior of the circuit variables for each switching state, along with a set of multi-objective control variables all in one cost function. The quasi impedance network and the AC load are considered together when designing the controller in order to obtain stability of the impedance network with a step change in the output reference. A detailed comparative investigation between the proposed controller and the conventional PI controller is presented to prove the superiority of the proposed method over the conventional control method. Simulation and experimental results are presented.
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