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Updates found with 'multilevel'

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Updates found with 'multilevel'

IEEE 2016 - 2017 Power Electronics and Power Systems Titles1) Investigation of Negative-Sequence Injection Capability of Cascaded H-Bridge Converters in Star and Delta Configuration2) A Novel Control for a Cascaded Buck Boost PFC Converter Operating in Discontinuous Capacitor Voltage Mode3) A Single-Phase Buck-Boost Matrix Converter with Only Six Switches and Without Commutation Problem4) Adaptive Neuro Fuzzy Inference System Least Mean Square Based Control Algorithm for DSTATCOM5) Average-Value Model of Modular Multilevel Converters Considering Capacitor Voltage Ripple6) LMF Based Control Algorithm for Single Stage Three-Phase Grid Integrated Solar PV System7) Analysis of bi-directional piezoelectric-based converters for zero-voltage switching operation8) A Multi-Level Converter with a Floating Bridge for Open-Ended Winding Motor Drive Applications9) Variable Duty Cycle Control for Quadratic Boost PFC Converter10) Pulse Pattern Modulated Strategy for Harmonic Current Components Reduction in Three-Phase AC-DC Converters11) Practical Layouts and DC-Rail Voltage Clamping Techniques of Z-Source Inverters12) A Low Capacitance Cascaded H-Bridge Multi-Level StatCom13) Impedance networks and its Application in Power for Electric Traction Systems14) Phase Current Balance Control Using DC-Link Current Sensor for Multi-Phase Converters with Discontinuous Current Mode Considered 15) Efficient Single Phase Transformerless Inverter for Grid-Tied PVG System With Reactive Power Control16) Single-Stage High Power Factor Converters Requiring Low DC-Link Capacitance to Drive Power LEDs17) High Efficiency Bi-Directional Converter for Flywheel Energy Storage Application18) Z-Source Resonant Converter with Power Factor Correction for Wireless Power Transfer Applications19) Design of External Inductor for Improving Performance of Voltage Controlled DSTATCOM20) A Single-Switch AC-DC LED Driver Based on a Boost-Flyback PFC Converter with Lossless Snubber21) Control and Analysis of the Modular Multilevel DC De-Icer with STATCOM Functionality22) Combined Phase Shift and Frequency Modulation of a Dual Active Bridge AC-DC Converter with PFC23) Least Power Point Tracking Method for Photovoltaic Differential Power Processing Systems24) Experimental Investigation on a Hybrid Series Active Power Compensator to Improve Power Quality of Typical Households25) Soft Start and Voltage Control of Induction Motors using Floating Capacitor Hbridge Converters26) High Performance Predictive Control of Quasi Impedance Source Inverter27) Analysis of the Integrated SEPIC-Flyback Converter as a Single-Stage Single-Switch Power-Factor-Correction LED Driver28) Matrix Converter Based Active Distribution Transformer29) Universal AC Input High Density Power Adapter Design with a Clamped Series Resonant30) SVM Strategies for Common-Mode Current Reduction in Transformerless Current-Source Drives at Low Modulation Index31) A Single-stage High Frequency Resonant AC/AC Converter32) Analysis and Control of Neutral-Point Voltage for Transformerless Three-Level PV Inverter in LVRT Operation33) A Hybrid-STATCOM with Wide Compensation Range and Low DC-Link Voltage34) A Single-Stage Single-Switch LED Driver Based on Class-E Converter35) Impedance Coordinative Control for Cascaded Converter in Bidirectional Application36) A DC-voltage Controlled Variable Capacitor for Stabilizing the ZVS Frequency of a Resonant Converter for Wireless Power Transfer37) Combined LMS-LMF Based Control Algorithm of DSTATCOM for Power Quality Enhancement in Distribution System38) Interleaved SEPIC Power Factor Pre-Regulator Using Coupled Inductors in Discontinuous Conduction Mode with Wide Output Voltage39) Model Predictive Control Scheme of Five-Leg AC-DC-AC Converter-Fed Induction Motor Drive40) A Virtual RLC Damper to Stabilize DC/DC Converters Having an LC Input Filter while Improving the Filter Performance41) Synchronous Power Controller with Flexible Droop Characteristics for Renewable Power Generation Systems42) A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction43) A Real-time Variable Turn-off Current Strategy for PFC Converter with Voltage Spike Limitation and Efficiency Improvement44) A Common Grounded Z-Source DC-DC Converter with High Voltage Gain45) A Digital Predictive Current Mode Controller for Single Phase High Frequency Transformer Isolated Dual Active Bridge DC to DC Converter46) A High-Voltage Compliant Current-to-Digital Sensor for DC-DC Converters in Standard CMOS Technology47) A New Single-Switch Isolated High-Gain Hybrid Boosting Converter48) A Novel Approach to Generate Effective Carrier-Based Pulsewidth Modulation Strategies for Diode-Clamped Multilevel DC-AC Converters49) A Novel Medium-Voltage Modular Multilevel DC-DC Converter50) A PWM Plus Phase-Shift Controlled Interleaved Isolated Boost Converter Based on Semi-Active Quadrupler Rectifier for High Step-Up Applications51) Analysis and Design of Current-Fed High Step Up PWM Controlled Quasi-Resonant DC-DC Converter for Fuel Cell Applications52) Analysis and Implementation of a Non-Isolated Bidirectional DC-DC Converter with High Voltage Gain53) Capacitor Aging Detection in DC-DC Converter Output Stage54) Derivation of Dual-Switch Step-Down DC/DC Converters with Fault-Tolerant Capability55) Design and Analysis of a High Efficiency DCDC Converter with Soft Switching Capability for Renewable Energy Applications Requiring High Voltage Gain56) Design and Steady State Analysis of Parallel Resonant DC-DC Converter for High Voltage Power Generator57) Digital Control of a High Voltage (2.5 kV) Bidirectional DC-DC Flyback Converter for Driving a Capacitive Incremental Actuator58) Downsizing Effects of Integrated Magnetic Components in High Power Density DC-DC Converters for EV and HEV59) Effective Voltage Balance Control for Bipolar-DC-Bus Fed EV Charging Station with Three-Level DC-DC Fast Charger60) Feed-Forward based Control in a DC-DC Converter of Asymmetric Multistage Stacked Boost Architecture61) High Step-Up/Step-Down Soft-Switching Bidirectional DC-DC Converter with Coupled-Inductor and Voltage Matching Control for Energy Storage Systems62) High-Efficiency Asymmetric Forward-Fly back Converter for Wide Output Power Range63) Isolated Double Step-down DC-DC Converter with Improved ZVS Range and No Transformer Saturation Problem64) Minimum-Current-Stress Scheme of Dual Active Bridge DC-DC Converter with Unified-phase-shift Control65) Model Predictive Control of Capacitor Voltage Balancing for Cascaded Modular DC-DC Converters66) Model Predictive Voltage Control for Single Inductor Multiple-Output DC-DC Converter with Reduced Cross Regulation67) Parasitics Assisted Soft-switching and Secondary Modulated Snubberless Clamping Current-fed Bidirectional Voltage Doubler for Fuel Cell Vehicles68) Stability Analysis and Stabilization methods of DC Microgrid with Multiple Parallel-Connected DC-DC Converters loaded by CPLs69) Steady-State Analysis of Inductor Conduction Modes in the Quadratic Boost Converter70) Suppression of the Peak Harmonics from Loads by Using a Variable Capacitance Filter in Low-Voltage DC/DC Converters71) Topology Derivation and Generalized Analysis of Zero-Voltage-Switching Synchronous DC-DC Converters with Coupled Inductors72) Unified Triple-Phase-Shift Control to Minimize Current Stress and Achieve Full Soft Switching of Isolated Bidirectional DC-DC Converter73) A New Transformerless Buck-Boost Converter With Positive Output Voltage74) Derivation of Dual-Switch Step-Down DC/DC Converters with Fault-Tolerant Capability75) Digital Sensorless Current Mode Control Based on Charge Balance Principle and Dual Current Error Compensation for DC–DC Converters in DCM
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POWER ELECTRONICS ABSTRACT 2016-2017 A LOW CAPACITANCE CASCADED H-BRIDGE MULTI-LEVEL STAT COM ABSTRACT:This paper introduces a cascaded H-bridge multilevel converter (CHB-MC) based Stat Com system that is able to operate with extremely low dc capacitance values. The theoretical limit is calculated for the maximum capacitor voltage ripple, and hence minimum dc capacitance values that can be used in the converter. The proposed low-capacitance Stat Com (LC-Stat Com) is able to operate with large capacitor voltage ripples, which are very close to the calculated theoretical maximum voltage ripple. The maximum voltage stress on the semiconductors in the LC-Stat Com is lower than in a conventional Stat Com system. The variable cluster voltage magnitude in the LC-Stat Com system drops well below the maximum grid voltage, which allows a fixed maximum voltage on the individual capacitors. It is demonstrated that the proposed LC-Stat Com has an asymmetric V-I characteristic, which is especially suited for operation as a reactive power source within the capacitive region. A high-bandwidth control system is designed for the proposed Stat Com to provide control of the capacitor voltages during highly dynamic transient events. The proposed LC-Stat Com system is experimentally verified on a low-voltage 7-level CHB-MC prototype. The experimental results show successful operation of the system with ripples as high as90% of the nominal dc voltage. The required energy storage for the LC-Stat Com system shows significant reduction compared to a conventional Stat Com design.
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VLSI PROJECTS ABSTRACT: 2016-2017 EXPLOITING INTRACELL BIT-ERROR CHARACTERISTICS TO IMPROVE MIN-SUM LDPC DECODING FOR MLC NAND FLASH-BASED STORAGE IN MOBILE DEVICE ABSTRACT: A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity challenge for NAND flash memory. This consequently makes the low-density parity-check (LDPC) code and the soft-decision memory sensing become indispensable in the next-generation flash-based solid-state storage devices. However, the use of LDPC codes inevitably increases memory read latency and, hence, degrades speed performance. Motivated by the observation of intracell unbalanced bit error probability and data dependence in the MLC NAND flash memory, this paper proposes two techniques, i.e., intracell data placement interleaving and intracell data dependence aware LDPC decoding, to efficiently improve the LDPC decoding throughput and energy efficiency for the MLC NAND flash-based storage in a mobile device. Experimental results show that, by exploiting the intracell bit-error characteristics, the proposed techniques together can improve the LDPC decoding throughput by up to 84.6% and reduce the energy consumption by up to 33.2% while only incurring less than 0.2% silicon area overhead. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.EXISTING SYSTEM: Compared with single-level cell, MLC NAND flash memory allows more bits to be stored in a single cell. As the penalty for its high storage density, each MLC NAND flash memory cell has much less margin between two adjacent storage states and is thereby much more prone to errors. In order to reduce its raw bit error probability, Gray code is commonly used when mapping information bits to voltage levels in the MLC cells, so that neighboring levels only differ in 1 bit. Fig. 1 shows an example for 2-bit/cell NAND flash memory. The voltage levels S0, S1, S2, and S3 denote information bits 11, 10, 00, and 01, respectively. The most significant bit (MSB) and the least significant bit (LSB) are associated with upper page and lower page, respectively.PROPOSED SYSTEM: This section describes the proposed techniques and VLSI architecture that exploit intracell bit-error characteristics to improve the throughput and energy efficiency of min-sum LDPC decoding for the MLC NAND flash-based solid-state storage in the mobile devices.The proposed intracell data placement interleaving technique is shown in Fig. 2. To make one codeword contain both the upper page bit and the lower page bit belonging to the same flash memory cell, we divide each codeword into several subblocks, and place the subblocks into upper page and lower page alternately in an interleaved form. In particular, the size of each subblock is chosen to be half of the parallel processing bits of an LDPC decoder, and thus, the decoder could process data that are stored in the same flash cells simultaneously. One potential benefit of the proposed intracell data placement interleaving technique is to reduce the hard-decision decoding failure rate. Due to intracell unbalanced bit error probability, to interleave data placement into both the upper and lower pages can significantly reduce the percentage of data pages that have relatively high BER, even though their average BER almost remains the same. ADVANTAGES:• reduce the number of decoding iteration• increase the error correction strengthDISADVANTAGES:• decoding iteration is high• error correction strength is lowSOFTWARE IMPLEMENTATION:• Modelsim• Xilinx ISE
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IEEE 2016 POWER ELECTRONICS ABSTRACTLCL FILTER DESIGN FOR THREE-PHASE TWO-LEVEL POWER FACTOR CORRECTION USING LINE IMPEDANCE STABILIZATION NETWORK ABSTRACT: These days, three-phase grid-connected PWM voltage source converters (VSCs) like two-level or multilevel converters are widely used in many applications. Trying to improve the power quality and attenuating the current harmonics generated by these converters leads to different approaches such as filter design and harmonic elimination/mitigation methods. To attenuate the harmonic contents at high frequencies one possible solution is relying on the inductor of three-phase boost VSC as a filter. Nevertheless, this solution leads to a bulky inductor with high power inductor losses. Besides, the large inductance value degrades the performance of the controller. Employing high order filters such as LCL, LLCL filters to fulfil the grid regulations are highly attractive solution and have been studied in many researchesEXISTING SYSTEM: The DC side of the rectifier consists of the DC capacitor and is connected to a load. Here, two LCL-filter configurations with different resonance frequencies are used. Choosing a higher filter capacitor yields to higher damping of the switching harmonics, but reduces the resonance frequency of the filter as it can be seen in the Bode diagram in Fig. 2.For the purpose of feedback the DC link voltage as well as the converter and line currents are measured. The line voltage is measured for synchronizing the control with the grid frequency. Here the space vector notation is used. The three-phase values are transformed into stationary reference frame and further, using the line voltage vector, into rotating dq coordinates in order to perform the voltage-oriented-control. From control point of view it is advantageous to control DC values since PI controllers can achieve reference tracking without steady state errors. As disadvantage the coordinate transformation leads to current dynamics coupling. PROPOSED SYSTEM: A method for designing an LCL filter for two-level PFCs using LISN. Using the equivalent circuit of the converter, the effect of LISN on measurement is studied. Filter parameters are, then, calculated by analyzing the equivalent circuit. In this paper, a passive damping method also is employed for improving the dynamic performance of the converter. Finally, a 5 kW three-phase PFC setup is used to verify the performance of the designed filter. The single-phase equivalent circuit not only simplifies designing the filter, but also helps to investigate the effect of LISN on circuit. To do that, the noise source must be defined. For an SPWM grid-connected VSC, using double Fourier analysis, the amplitude of ac link voltage at multiples of switching frequency (carrier frequency).ADVANTAGES:• Improved dynamic performance.• Low impedance network for the high frequency harmonics. APPLICATIONS:• High and low power applications.• Silicon-carbides (SiCs).
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