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Updates found with 'signal paths'

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Updates found with 'signal paths'

VLSI PROJECTS ABSTRACT 2016-2017 A FULLY DIGITAL FRONT-END ARCHITECTURE FOR ECG ACQUISITION SYSTEM WITH 0.5 V SUPPLY ABSTRACT: This paper presents a new power-efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area. The proposed architecture is compatible with digital CMOS technology and is capable of operating with a low supply voltage of 0.5 V. In this architecture, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive elements, such as ac coupling capacitors, are used. A moving average voltage-to time converter is used, which behaves instead of the LNA and anti-aliasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, which eliminates the need for coupling capacitors. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. EXISTING SYSTEM A digital signal processor then processes the digital data for monitoring or diagnosis applications. Biomedical signal acquisition systems typically consist of a low-noise amplifier (LNA), a bandpass filter, an analog sample-and-hold, and an analog-to-digital converter (ADC), as shown in Fig. 1(a). While the architecture shown in Fig. 1(a) is typically used, in some cases chopping technique is used to reduce the impact of the flicker noise, as shown in Fig. 1(b). PROPOSED SYSTEM: Fig. 3(a) shows the block diagram of the proposed fully digital architecture. In this structure, the processing of the bio-signal is performed in the time and digital domain. Hence, the advantages of digital CMOS technology are utilized. The analog bio-signal coming from the electrode is directly connected to the front-end circuit and is converted to time with a voltage-to-time converter (VTC). From this point on in the circuit, the signal information is in the phase of the VTC output signal. The output of the VTC is applied to the time-mode processing block, in which the anti-aliasing and offset cancellation are done in time domain. Then, a time-to-digital converter (TDC) transfers the time-mode signal into digital domain where other processes (digital filtering, data compression/reduction and so on) are performed. ADVANTAGES:• Compact • Low power consumption DISADVANTAGES:• Power consumption is high• Coverage area is high SOFTWARE IMPLEMENTATION• Modelsim• Xilinx ISE
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VLSI PROJECTS ABSTRACT 2016-2017 A HIGH-SPEED FPGA IMPLEMENTATION OF AN RSD-BASED ECC PROCESSOR ABSTRACT: In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba–Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.EXISTING SYSTEM: In prime field ECC processors, carry free arithmetic is necessary to avoid lengthy datapaths caused by carry propagation. Redundant schemes, such as carry save arithmetic (CSA), redundant signed digits (RSDs) , or residue number systems (RNSs) , have been utilized in various designs. Carry logic or embedded digital signal processing (DSP) blocks within fieldprogrammable gate arrays (FPGAs) are also utilized in some designs to address the carry propagation problem. It is necessary to build an efficient addition data path since it is a fundamental operation employed in other modular arithmetic operations. Modular multiplication is an essential operation in ECC. PROPOSED SYSTEM: The proposed P256 ECC processor consists of an AU of 256 RSD digit wide, a finite-state machine (FSM), memory, and two data buses. The processor can be configured in the pre-synthesis phase to support the P192 or P224 NIST recommended prime curves [36]. Fig. 1 shows the overall processor architecture. Two sub control units are attached to the main control unit as add-on blocks. These two sub control units work as FSMs for point addition and point doubling, respectively. Different coordinate systems are easily supported by adding corresponding sub control blocks that operate according to the formulas of the coordinate system. ADVANTAGES:• short data paths • increased maximum frequency SOFTWARE IMPLEMENTATION:• Modelsim• Xilinx ISE
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VLSI PROJECTS ABSTRACT 2016-2017 A NORMAL I/O ORDER RADIX-2 FFT ARCHITECTURE TO PROCESS TWIN DATA STREAMS FOR MIMO ABSTRACT: Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. EXISTING SYSTEM: There are FFT architectures, which can handle multiple independent data streams. However, all the data streams are processed by a single FFT processor. In four independent data streams are processed one by one. Similarly, eight data streams are processed at two domains. Thus, the outputs of multiple data streams are not available in parallel. In order to simultaneously process the data streams, more than one FFT processors need to be employed. In one to four data streams are processed using multiple data paths for wireless local area network application. Data of different data streams are interleaved to process them simultaneously. In low complexity FFT architectures are proposed but these architectures can process only real-valued signals (signals only with real part). Moreover, they generate two outputs per clock cycle and these outputs are not in natural order. Thus, most of the recent architectures require bit reversal structures to generate the outputs in natural order. PROPOSED SYSTEM: The idea of computing an N-point FFT using two N/2-point FFT operations with additional one stage of butterfly operations is shown in Fig. 1, which is not the exact architecture but provides the methodology. The reordering blocks in Fig. 1 are merely present to state that the N/2 odd samples (x(2n + 1)) are reordered before the N/2-point DIT FFT operation and N/2 even samples (x(2n)) are reordered after the N/2-point DIF FFT operation. In order to compute the N-point DIT FFT from the outputs of two N/2-point FFTs, additional one stage of butterfly operations are performed on the results of the two FFTs. Thus, the outputs generated by additional butterfly stage are in natural order.ADVANTAGES:• throughput high• high performance• reduce the usage of hardware elementDISADVANTAGES:• Performance is low• usage of hardware element is highSOFTWARE IMPLEMENTATION• Modelsim• Xilinx ISE
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VLSI PROJECTS ABSTRACT: 2016-2017 A LOW-POWER ROBUST EASILY CASCADED PENTAMTJ-BASED COMBINATIONAL AND SEQUENTIAL CIRCUITS ABSTRACT: Advanced computing systems embed spintronic devices to improve the leakage performance of conventional CMOS systems. High speed, low power, and infinite endurance are important properties of magnetic tunnel junction (MTJ), a spintronic device, which assures its use in memories and logic circuits. This paper presents a PentaMTJ-based logic gate, which provides easy cascading, self-referencing, less voltage headroom problem in precharge sense amplifier and low area overhead contrary to existing MTJ-based gates. PentaMTJ is used here because it provides guaranteed disturbance free reading and increased tolerance to process variations along with compatibility with CMOS process. The logic gate is validated by simulation at the 45-nm technology node using a Verilog A model of the PentaMTJ. The proposed architecture of this paper area and power consumption analysis using HSpice.Existing System: SPINTRONICS has been under extensive research because of nonvolatility, infinite endurance, and low power. The spin is employed for storing information and the charge for its processing. It has the potential to replace CMOS logic and memory. In deep submicrometer, scaling of CMOS causes the leakage power to dominate over all other power components. Digital signals are represented in conventional CMOS logic by the presence or absence of electrical charge in terms of voltage VDD or ground. However, in Spintronics, digital signals are represented by up and down spin of electron. In recent years, researchers have developed spintronic devices, such as magnetic tunnel junctions (MTJs), which operates on the principle of tunnel magneto resistance (TMR). An MTJ is composed of two ferromagnetic layers separated by an oxide layer with the capability to improve the performance of CMOS logic circuit in terms of power dissipation, area required, and interconnection delay. It can also be easily fabricated using 3-D backend integration process, which is compatible with CMOS process, without any area overhead. PROPOSED SYSTEM: Fig. 1 shows the structure of the PentaMTJ which comprises of two pinned layers: 1) top pinned layer (TPL) and 2) bottom pinned layer (BPL). The magnetization of two pinned layers is in opposite direction and is fixed. In this paper, 1 state is assigned when TPL (pinned 1) is parallel to the free layer and 0 states when BPL (pinned 2) is parallel to the free layer. The proposed structure of PentaMTJ needs less current for writing as compared with the conventional MTJ. It requires current only for converting anti-parallel to parallel state for one stack, the other stack automatically comes into anti-parallel state. Moreover, PentaMTJ provides guaranteed disturbance free reading and increases the tolerance to process variation as per the only reference available in the literature on PentaMTJ. ADVANTAGES• no extra hardware is needed for complementary outputs• no need to initialize the state of the output MTJ for sensingSOFTWARE IMPLEMENTATION• Hspice
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JAVA /DOT NET PROJECTS ABSTRACT 2016-2017 INTELLIGENT HANDS FREE SPEECH BASED SMS SYSTEM ON ANDROID ABSTRACT: Over the years speech recognition has taken the market. The speech input can be used in varying domains such as automatic reader and for inputting data to the system. Speech recognition can minimize the use of text and other types of input, at the same time minimizing the calculation needed for the process. Decade back speech recognition was difficult to use in any system, but with elevation in technology leading to new algorithms, techniques and advanced tools. Now it is possible to generate the desired speech recognition output. One such method is the hidden markov models which is used in this paper. Voice or signaled input is inserted through any speech device such as microphone, then speech can be processed and convert it to text hence able to send SMS, also Phone number can be entering either by voice or you may select it from contact list. Voice has opened up data input for a variety of user’s such as illiterate, Handicapped, as if the person cannot write then the speech input is a boon and other’s too which Can lead to better usage of the application. This application also included that user can only input numeric character for contact information, i.e. the security validation for number is done. SR will listen to input and convert numeric to text and will be displayed on contact information to verify. If any user try to insert any other character into the information an error would be displayed e.g. if user speaks his name for contact, it will be displayed as invalid contact. The message box can accept any character. To use the speech recognition user has to be loud and clear so that command is properly executed by the system.SYSTEM SPECIFICATION:HARDWARE REQUIREMENTS: System : Pentium IV 2.4 GHz. Hard Disk : 40 GB. Floppy Drive : 1.44 Mb. Monitor : 14’ Colour Monitor. Mouse : Optical Mouse. Ram : 512 Mb.SOFTWARE REQUIREMENTS: Operating system : Windows 7 Ultimate. Coding Language : Java. Front-End : Eclipse. Data Base : Sqlite Manger.Conclusion: An automatic speech recognizer studied and implemented on the android platform which gives much accuracy for both numeric and alpha numeric inputs. Developed Speech recognizer system tested for a SMS sending application and found that it recognizes the speech to an accuracy of more than 90%. Enter phone number by speech or select contact from contact list. As user presses select contact here by selecting name of person it gives all phone numbers of that person in phone contact list box. Now it is possible to send sms to all numbers of same person on one click which results in reducing time of searching each number. The accuracy of this system is about 90%, and delay for recognition is less than 100 ns. This system tested for various speakers which had varying speech speed, amplitude and frequency. The results of this system are very good and recognized most of the speech inputs. We plan to implement this work for other languages as well as test them on the SMS sending application which is developed.
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VLSI PROJECTS ABSTRACT 2016-2017: A CELLULAR NETWORK ARCHITECTURE WITH POLYNOMIAL WEIGHT FUNCTIONS ABSTRACT: Emulations of cellular nonlinear networks on digital reconfigurable hardware are renowned for an efficient computation of massive data, exceeding the accuracy and flexibility of full-custom designs. In this contribution, a digital implementation with polynomial coupling weight functions is proposed for the first time, establishing novel fields of application, e.g., in the medical signal processing and in the solution of partial differential equations. We present an architecture that is capable of processing large-scale networks with a high degree of parallelism, implemented on state-of-the-art field-programmable gate arrays. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. EXISTING SYSTEM: The precision of analog implementations is usually not sufficient for numerically sophisticated applications. Moreover, the design of these application specific integrated circuits (ASICs) is generally fixed and parameters like network size or data precision cannot be adjusted. Thus, the emulation of CNNs on reconfigurable digital devices, especially on field-programmable gate arrays (FPGAs), becomes attractive for prototyping and applications where flexibility and/or higher precision is required. PROPOSED SYSTEM: A direct mapping of the cellular network structure to digital hardware is feasible and efficient, yet strongly limited by the available resources. For that reason, we designed the NERO architecture by mapping large-scale networks to medium- or small-scale processor arrays, yet retaining the local couplings of the CNN paradigm and minimizing the number and length of interconnections between the PEs. :ADVANTGES: • System efficiency is less DISADVANTAGES: • System efficiency is less SOFTWARE IMPLEMENTATION: • Modelsim • Xilinx ISE
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VLSI PROJECTS ABSTRACT 2016-2017 A HIGH THROUGHPUT LIST DECODER ARCHITECTURE FOR POLAR CODES ABSTRACT: While long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless channels when decoded by a low complexity successive-cancellation (SC) algorithm, the error performance of the SC algorithm is inferior for polar codes with finite block lengths. The cyclic redundancy check (CRC)-aided SC list (SCL) decoding algorithm has better error performance than the SC algorithm. However, current CRC-aided SCL decoders still suffer from long decoding latency and limited throughput. In this paper, a reduced latency list decoding (RLLD) algorithm for polar codes is proposed. Our RLLD algorithm performs the list decoding on a binary tree, whose leaves correspond to the bits of a polar code. In existing SCL decoding algorithms, all the nodes in the tree are traversed, and all possibilities of the information bits are considered. Instead, our RLLD algorithm visits much fewer nodes in the tree and considers fewer possibilities of the information bits. When configured properly, our RLLD algorithm significantly reduces the decoding latency and, hence, improves throughput, while introducing little performance degradation. Based on our RLLD algorithm, we also propose a high throughput list decoder architecture, which is suitable for larger block lengths due to its scalable partial sum computation unit. Our decoder architecture has been implemented for different block lengths and list sizes using the TSMC 90-nm CMOS technology. The implementation results demonstrate that our decoders achieve significant latency reduction and area efficiency improvement compared with the other list polar decoders in the literature. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. EXISTING SYSTEM: Despite its significantly improved error performance, the hardware implementations of SC-based list decoders [7]–[11] still suffer from long decoding latency and limited throughput due to the serial decoding schedule. In order to reduce the decoding l atency of an SC-based list decoder, M (M > 1) bits are decoded in parallel in [12]–[14], where the decoding speed can be improved by M times ideally. However, for the hardware implementations of the algorithms in [12]–[14], the actual decoding speed improvement is less than M times due to extra decoding cycles on finding the L most reliable paths among 2M L candidates, where L is the list size. A software adaptive simplified SC (SSC)-list-CRC decoder was proposed in [15]. For a (2048, 1723) polar + CRC-32 code, the SSC-list-CRC decoder with L = 32 was shown to be about seven times faster than an SC-based list decoder. However, it is unclear whether the list decoder in [15] is suitable for hardware implementation.PROPOSED SYSTEM: In this paper, an RLLD algorithm is proposed to reduce the decoding latency of SC list decoding for polar codes. For a node v, let Iv denote the total number of leaf nodes that are associated with information bits. Let Xth be a predefined threshold value and X0 and X1 be predefined parameters.Moreover, our RLLD algorithm works on a pruned tree. As a result, our RLLD algorithm visits fewer nodes than the SCL algorithm. The full binary tree is pruned in two steps.1) Step 1: Starting from the complete tree representation of a polar code, label all FP nodes such that the parent node of each of them is not an FP node. For each labeled FP node, remove all its child nodes. 2) Step 2: Based on the pruned tree from Step 1, label all rate-0 and rate-1 nodes such that the parent node of each of these rate-0 and rate-1 nodes is not a rate-0 and rate-1 node, respectively. In the next, remove all child nodes of each of a labeled rate-0 and rate-1 node.ADVANTAGES:• reduce the decoding latency• reduce the size of message memories DISADVANTAGES:• the size of message memories are large SOFTWARE IMPLEMENTATION• Modelsim• Xilinx ISE
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VLSI PROJECTS ABSTRACT 2016-2017 A HIGH-PERFORMANCE FIR FILTER ARCHITECTURE FOR FIXED AND RE CONFIGURABLE APPLICATIONS ABSTRACT: Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose form configuration for area-delay efficient realization of large order FIR filters for both fixed and reconfigurable applications. Based on a detailed computational analysis of transpose form configuration of FIR filter, we have derived a flow graph for transpose form block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose form FIR filter. We have derived a general multiplier-based architecture for the proposed transpose form block filter for reconfigurable applications. A low-complexity design using the MCM scheme is also presented for the block implementation of fixed FIR filters. The proposed structure involves significantly less area delay product (ADP) and less energy per sample (EPS) than the existing block implementation of direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure. Application specific integrated circuit synthesis result shows that the proposed structure for block size 4 and filter length 64 involves 42% less ADP and 40% less EPS than the best available FIR filter structure proposed for reconfigurable applications. For the same filter length and the same block size, the proposed structure involves 13% less ADP and 12.8% less EPS than those of the existing direct-form block FIR structure. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. PROPOSED SYSTEM: In phase 1 to discussed about 16 tap FIR filter for Low pass, High pass, Band pass, and band stop filter and to analysis the performance, efficiency, speed, and power consumption for the respective filter types. Fig.6 shows the block diagram of the proposed system. The NCO used for signal generation with required frequency range. NCO is used in the modulation block. ADVANTAGES:• reduced filter length• less element to used• reduced cycle period DISADVANTAGES• element usage is high• cycle period is highSOFTWARE IMPLEMENTATION• Modelsim• Xilinx 14.2
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VLSI PROJECTS ABSTRACT 2016-2017 A SINGLE-ENDED WITH DYNAMIC FEEDBACK CONTROL 8T SUBTHRESHOLD SRAM CELL ABSTRACT: A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of 1.4× and 1.28× as that of isoarea 6T and read-decoupled 8T (RD-8T), respectively, at 300 mV. The standard deviation of write SNM for 8T cell is reduced to 0.4× and 0.56× as that for 6T and RD-8T, respectively. It also possesses another striking feature of high read SNM ∼2.33×, 1.23×, and 0.89× as that of 5T, 6T, and RD-8T, respectively. The cell has hold SNM of 1.43×, 1.23×, and 1.05× as that of 5T, 6T, and RD-8T, respectively. The write time is 71% lesser than that of single-ended asymmetrical 8T cell. The proposed 8T consumes less write power 0.72×, 0.6×, and 0.85× as that of 5T, 6T, and isoarea RD-8T, respectively. The read power is 0.49× of 5T, 0.48× of 6T, and 0.64× of RD-8T. The power/energy consumption of 1-kb 8T SRAM array during read and write operations is 0.43× and 0.34×, respectively, of 1-kb 6T array. These features enable ultralow power applications of 8T. The proposed architecture of this paper area and power consumption analysis using tanner tool.Existing System: The portable microprocessor controlled devices contain embedded memory, which represents a large portion of the system-on-chip (SoC). These portable systems need ultralow power consuming circuits to utilize battery for longer duration. The power consumption can be minimized using nonconventional device structures, new circuit topologies, and optimizing the architecture. Although, voltage scaling has led to circuit operation in subthreshold regime with minimum power consumption, but there is a disadvantage of exponential reduction in performance. The circuit operation in the subthreshold regime has paved path toward ultralow power embedded memories, mainly static RAMs (SRAMs). However, in subthreshold regime, the data stability of SRAM cell is a severe problem and worsens with the scaling of MOSFET to subnanometer technology. Due to these limitations it becomes difficult to operate the conventional 6-transistor (6T) cell at ultralow voltage (ULV) power supply. In addition, 6T has a severe problem of read disturb. The basic and an effective way to eliminate this problem is the decoupling of true storing node from the bit lines during the read operation. This read decoupling approach is utilized by conventional 8-transistor [read decoupled 8-transistor (RD-8T)] cell which offers read static noise margin (RSNM) comparable with hold static noise margin (HSNM). However, RD-8T suffers from leakage introduced in read path. This leakage current increases with the scaling thereby, increasing the probability of failed read/write operations. Similar cells that maintain the cell current without disturbing the storage node are also proposed.Proposed System: To make a cell stable in all operations, single-ended with dynamic feedback control (SE-DFC) cell is presented in Fig. 1(a). The single-ended design is used to reduce the differential switching power during read–write operation. The power consumed during switching/ toggling of data on single bit line is lesser than that on differential bit-line pair. The SE-DFC enables writing through single nMOS in 8T. It also separates the read and write path and exhibits read decoupling. The structural change of cell is considered to enhance the immunity against the process–voltage–temperature (PVT) variations. It improves the static noise margin (SNM) of 8T cell in subthreshold/near-threshold region. The proposed 8T has one cross coupled inverter pair, in which each inverter is made up of three cascaded transistors. These two stacked cross-coupled inverters: M1–M2–M4 and M8–M6–M5 retain the data during hold mode. The write word line (WWL) controls only one nMOS transistor M7, used to transfer the data from single write bit line (WBL). A separate read bit line (RBL) is used to transfer the data from cell to the output when read word line (RWL) is activated. Two columns biased feedback control signals: FCS1 and FCS2 lines are used to control the feedback cutting transistors: M6 and M2, respectively.ADVANTAGES:• higher power saving capability during read/write operations• higher Static Noise MarginDISADVANTAGES:• Low SNM• High power consumption SOFTWARE IMPLEMENTATION:• Tanner tools
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