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Home All Updates (3681) VLSI PROJECTS ABSTRA
VLSI PROJECTS ABSTRA
VLSI PROJECTS ABSTRACT 2016-2017 NEW FAST AND AREA-EFFICIENT ADDER-BASED SIGN DETECTOR FOR RNS 2n 12n 2n+1 ABSTRACT: The moduli set {2n-1, 2n, 2n+1} have been widely used in residue number system (RNS)-based computations. Its sign extraction problem, albeit fundamentally important in magnitude comparison and other difficult algorithms in RNS, has received considerably less attention than its scaling and reverse conversion problems. This brief presents a new algorithm for the design of a fast adder-based sign detector. The circuit is greatly simplified by shrinking the dynamic range to eliminate large modulo operations with the help of the new Chinese remainder theorem. Our synthesis results with the 65-nm CMOS standard cell library show that the proposed design outperforms all the existing adder-based sign detectors reported for this moduli set in area and speed for n rangesfrom5to25inthestepof5.
  • 2016-07-05T06:05:00

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