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Home All Updates (3681) VLSI PROJECTS ABSTRA
VLSI PROJECTS ABSTRA
VLSI PROJECTS ABSTRACT 2016-2017 HIGH-SPEED, LOW-POWER, AND HIGHLY RELIABLE FREQUENCY MULTIPLIER FOR DLL-BASED CLOCK GENERATOR ABSTRACT: A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz–3.3 GHz. The frequency multiplier achieves power consumption to a frequency ratio of 2.9µW/MHz. The proposed architecture of this paper area and power consumption analysis using tanner tool. EXISTING SYSTEM: Fig. 1 shows the structures of the recently published frequency multipliers that perform better than most previous frequency multipliers. The frequency multiplier is composed of a D-flip–flop-based pulse generator, multiplication-ratio control logic, and a push–pull-stage based edge combiner, as shown in Fig. 1(a). Owing to its simple edge-combiner structure, this frequency multiplier is suitable for high-frequency multiplied clock generation with low power and a small area. Fig. 1(b) shows the structure of another frequency multiplier. This frequency multiplier is composed of multiplication-ratio control logic, an AND-gate-based pulse generator, and a differential cascade voltage switch (SW) logic (DCVSL)-stage-based edge combiner. The frequency multiplier can generate the multiplied differential clocks with a small area penalty. PROPOSED SYSTEM The proposed DLL-based clock generator is composed of a DLL core and the proposed frequency multiplier, as shown in Fig. 2. To enhance the lock time, which is an important design parameter in the clock generator, a dual-edge-triggered phase-detector-based DLL core is adopted. Similar to previous frequency multipliers, the proposed frequency multiplier is also composed of a pulse generator, multiplication-ratio control logic, and an edge combiner. ADVANTAGES: • Reduce the delay DISADVANTAGES: • Speed is less SOFTWARE IMPLEMENTATION: • Tanner tools
  • 2016-07-15T10:20:46

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