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Home All Updates (3681) VLSI PROJECTS ABSTRA
VLSI PROJECTS ABSTRA
VLSI PROJECTS ABSTRACT 2016-2017 LOW-POWER VARIATION-TOLERANT NONVOLATILE LOOKUP TABLE DESIGN ABSTRACT: Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large ROFF/RON, 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RON or ROFF in reliability are achieved for proposed nvLUT with six inputs. The proposed architecture of this paper area and power consumption analysis using tanner tool. EXISTING SYSTEM: Emerging NVMs, such as MRAM, PRAM, and RRAM, has been verified with better scalability and logic compatibility. Based on the logic-in-memory concept, lookup table, which is the core building block in FPGAs, has been proposed with non-volatility. First, various nonvolatile SRAM (nvSRAM) structures with MRAM and RRAM were proposed to directly replace SRAM in the traditional lookup table to acquire non-volatility. However, the size of nvSRAM cell is remarkably larger than that of SRAM, and the write disturbance is also difficult to avoid for half-select RRAM cells. For MRAM, Suzuki et al. proposed a two-input nonvolatile lookup table (nvLUT) based on MRAM in the current-mode logic for low power. Suzuki et al. also proposed a six-input nvLUT with serial/parallel magnetic junctions to acquire enough sensing margin. Zhao et al. proposed another MRAM-based nvLUT for run-time reconfiguration. Ren proposed a third type of MRAM-based nvLUT named hybrid-LUT2. However, the ROFF/RON of MRAM is smaller compared with PRAM or RRAM, resulting in less sense margin or larger area due to serial/parallel magnetic junctions. PROPOSED SYSTEM To illustrate the proposed design, a two-input nvLUT is presented, as shown in Fig. 1. The input count can also be easily extended to six, which is prevailing in current main-stream FPGA products. The overall architecture of nvLUT consists of an SSAVC, a tree multiplexer (TMUX), an MRP, a RRAM slice, and a footer transistor. The RRAM slice constitutes of four 1T1R RRAM cells at the left for configuration and a dummy RRAM cell at the right-most as a reference resistor. ADVANTAGES: • reduce the parasitic RC mismatch • reduce the power DISADVANTAGES: • high parasitic RC mismatch • high power consumption SOFTWARE IMPLEMENTATION: • Tanner tools
  • 2016-07-16T07:27:38

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